m05e01 done

module05/ex01/timer.c

@@ -0,0 +1,22 @@
+#include "header.h"
+
+// Set up Timer1 in CTC mode to trigger every 20ms
+// With 16MHz clock and prescaler of 64, and OCR1A = 49999:
+// 16000000/64/50000 = 20ms period
+
+#define T1B_PRESCALE_VALUE	64
+
+void timer_1B_init() {
+	TCCR1A = 0;											// 16.11.1 : Normal operation, OC1A/OC1B disconnected
+	TCCR1B = CTC_TOP_OCR1A_IN_TCCR1B;					// 16.11.2 : CTC mode top OCR1A
+	TCCR1B |= T1_PRESCALE_SET(T1B_PRESCALE_VALUE);		// 16.11.2 : prescaler
+
+	OCR1A = TIME_MS(20, T1B_PRESCALE_VALUE);			// 16.11.5 : Compare match value for register A
+	OCR1B = 0;											// 16.11.6 : Compare match value for register B, if not defined, should default to 0
+
+	TIMSK1 = (1 << OCIE1B);								// 16.11.8 : Enable Timer1 Compare B Match Interrupt
+}
+
+ISR(TIMER1_COMPB_vect) {
+    // Empty ISR to ensure proper flag clearing or something like that (p145 : "OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed")
+}