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hugo LAMY
2025-03-14 20:48:14 +01:00
committed by hugogogo
parent b12eff7ede
commit 4c36e4e775
2 changed files with 15 additions and 8 deletions
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13
module05/ex00/timer.c
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@@ -3,10 +3,15 @@
// Set up Timer1 in CTC mode to trigger every 20ms
// With 16MHz clock and prescaler of 8, and OCR1A = 39999:
// 16MHz/8/40000 = 50Hz = 20ms period
#define T1B_PRESCALE_VALUE 64
void timer_1B_init() {
TCCR1A = 0; // Normal operation, OC1A/OC1B disconnected
TCCR1B = (1 << WGM12) | (1 << CS11); // CTC mode, prescaler = 8
OCR1A = 39999; // Compare match value for 20ms
TCCR1A = 0; // 16.11.1 : Normal operation, OC1A/OC1B disconnected
TCCR1B = (1 << WGM12); // 16.11.2 : CTC mode
TCCR1B |= T1_PRESCALE_SET(T1B_PRESCALE_VALUE); // 16.11.2 : prescaler = 8
OCR1A = TIME_MS(20, T1B_PRESCALE_VALUE); // 16.11.5 : Compare match value for register A
OCR1B = TIME_MS(20, T1B_PRESCALE_VALUE) - 1000; // 16.11.6 : Compare match value for register B
TIMSK1 = (1 << OCIE1B); // Enable Timer1 Compare B Match Interrupt
// TIMSK1 = (1 << OCIE1B); // Enable Timer1 Compare B Match Interrupt
// ADCSRA |= (1 << ADSC); // 24.9.2 : start first conversion
}