first version m05e00
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@@ -15,6 +15,10 @@
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// PROTOTYPES
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//
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// main.c
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// uart.c
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void uart_init();
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void uart_tx(char c);
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void uart_printstr(const char* str);
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//
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// MACROS
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@@ -1,6 +1,56 @@
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#include "header.h"
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// Table 14-6. Port C Pins Alternate Functions
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// - PC0 -> ADC0 (ADC Input Channel 0)
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// -> PCINT8 (Pin Change Interrupt 8)
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//
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// 24.2 : The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL
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#define INT_TO_HEX_CHAR(n) ((n) < 10 ? ('0' + (n)) : ('A' + ((n) - 10)))
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void int_to_hex_string(uint64_t value, char *out, uint8_t num_digits) {
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for (uint8_t i = 0; i < num_digits; ++i) {
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uint8_t shift = (num_digits - 1 - i) * 4;
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out[i] = INT_TO_HEX_CHAR((value >> shift) & 0x0F);
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}
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out[num_digits] = '\0';
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}
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void word_to_hex(uint16_t value, char *out) {
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out[0] = INT_TO_HEX_CHAR((value >> 8) & 0x0F);
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out[1] = INT_TO_HEX_CHAR((value >> 4) & 0x0F);
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out[2] = INT_TO_HEX_CHAR(value & 0x0F);
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out[3] = '\0';
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}
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void adc_init() {
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ADMUX = (1 << REFS0); // AVcc reference, ADC0
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ADCSRA = (1 << ADEN) // Enable ADC
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| (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0); // Prescaler = 128
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}
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uint16_t adc_read(uint8_t channel) {
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ADMUX = (ADMUX & 0xF0) | (channel & 0x0F); // Select ADC channel
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ADCSRA |= (1 << ADSC); // Start conversion
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while (ADCSRA & (1 << ADSC)); // Wait for completion
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return ADC;
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}
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// description
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int main() {
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while(1);
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char buffer[4];
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SREG |= ENABLE_GLOBAL_INTERRUPT; // 7.3.1 : Status Register, bit 7 : I – Global Interrupt Enable
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uart_init();
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adc_init();
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while(1) {
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uint16_t value = adc_read(0); // Read from ADC0 (A0)
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// snprintf(buffer, sizeof(buffer), "ADC: %u\r\n", value);
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word_to_hex(value, buffer);
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uart_printstr(buffer);
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uart_printstr("\r\n");
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_delay_ms(20); // Wait 20ms
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}
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}
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// ISR(ADC_vect) { // Table 12-6 : interrupt vector for ADC Conversion Complete
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// }
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72
module05/ex00/uart.c
Normal file
72
module05/ex00/uart.c
Normal file
@@ -0,0 +1,72 @@
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#include "header.h"
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// MACROS
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// USART
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#define USART_BAUDRATE 115200
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#define INPUT_SIZE 7
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// GLOBAL VARIABLES
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//
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// FUNCTIONS
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//
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void uart_init() {
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UBRR0H = (unsigned char) (BAUD_PRESCALER(USART_BAUDRATE) >> 8); // 20.11.5 : UBRRnL and UBRRnH – USART Baud Rate Registers
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UBRR0L = (unsigned char) BAUD_PRESCALER(USART_BAUDRATE);
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UCSR0C = DATA_EIGHT_BIT; // 20.11.4 : set Frame Format
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UCSR0B = TRANSMITTER_ENABLED; // 20.11.3 : enable Receiver, Transmitter, and interrupts
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}
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// char uart_rx(void) {
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// while (!TEST(UCSR0A, RXC0)); // 20.11.2 : do nothing until there are unread data in the receive buffer (UDRn), (RXCn flag in UCSRnA register set to 1 when buffer has data)
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// return UDR0; // 20.11.1 : get data in buffer, UDRn – USART I/O Data Register (read and write)
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// }
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void uart_tx(char c) {
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while (!TEST(UCSR0A, UDRE0)); // 20.11.2 : do nothing until UDRn buffer is empty, (UDREn flag in UCSRnA register set to 1 when buffer empty)
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UDR0 = (unsigned char) c; // 20.11.1 : Put data into buffer, UDRn – USART I/O Data Register (read and write)
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}
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void uart_printstr(const char* str) {
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while (*str) {
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uart_tx(*str);
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str++;
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}
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}
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// ISR(USART_RX_vect) { // Table 12-6 : we select the code for USART Receive
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// char received_char = UDR0; // read received character
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// if (received_char == '\b' || received_char == 127) { // if backspace is received
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// if (input_index <= 0) {
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// return;
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// }
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// if (input_index >= INPUT_SIZE) {
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// return;
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// }
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// remove_last_character();
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// input_index--;
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// uart_tx('\b'); // Move cursor back
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// uart_tx(' '); // Erase the character on screen
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// uart_tx('\b'); // Move cursor back again
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// } else if (received_char == '\n' || received_char == '\r') { // if enter is received
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// if (input_index != INPUT_SIZE) {
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// return;
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// }
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// set_color((char *)color_input);
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// reset_input();
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// } else { // any other character
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// if (input_index >= INPUT_SIZE) {
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// return;
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// }
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// if (!is_valid_color_input(received_char)) {
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// return;
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// }
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// fill_str(received_char);
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// uart_tx(received_char);
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// input_index++;
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// }
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// }
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// ISR(USART_TX_vect) { // Table 12-6 : we select the code for USART Transmit
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// char received_char = UDR0; // read received character
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// }
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2
rush00
2
rush00
Submodule rush00 updated: 4afab54715...e4ea057ebf
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