42/42_EXT_03_42chips
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

update comments

Browse Source
This commit is contained in:
hugogogo
2025-03-05 18:09:26 +01:00
parent 670e5f1f5e
commit 1e02176100
2 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
module01/ex00/main.c
View File

@@ -53,11 +53,11 @@ int main() {
TURN_OFF_LED(D2);
TCCR1B |= (PRESCALE_SET); // set timer with prescale
// -> set timer with bits CS10-12, in register TCCR1B : 16.4 Timer/Counter Clock Sources
// -> prescale values : table 16-5. Clock Select Bit Description
// -> 16.4 : set timer with bits CS10-12, in register TCCR1B
// -> table 16-5 : prescale values
while(1) {
if (TCNT1 >= TIME_MS(500)) { // read timer with register TCNT1 (read/write allowed), that combines two 8 bits registers : 16.11.4 TCNT1H and TCNT1L – Timer/Counter1
if (TCNT1 >= TIME_MS(500)) { // 16.11.4 : read timer with register TCNT1 (read/write allowed), that combines two 8 bits registers
TOGGLE_LED(D2);
TCNT1 = 0; // reset timer value, also in register TCNT1
}

12
module01/ex01/main.c
View File

@@ -52,23 +52,23 @@ int main() {
MODE_OUTPUT(B, D2);
TCCR1B |= (1 << WGM12); // set timer in CTC (Clear Time on Compare) mode
// -> use bit WGM12 to set mode ctc : Table 16-4. Waveform Generation Mode Bit Description
// -> bit WGM12 is located in register TCCR1B : 16.11.2 TCCR1B Timer/Counter1 Control Register B
// -> Table 16-4 : use bit WGM12 to set mode ctc
// -> 16.11.2 : bit WGM12 is located in register TCCR1B
OCR1A = TIME_MS(500); // set CTC compare value
// -> the value to reset the timer is the Output Compare Registers OCR1A : Table 16-4. Waveform Generation Mode Bit Description
// -> Table 16-4 : the value to reset the timer is the Output Compare Registers OCR1A
TCCR1B |= (PRESCALE_SET);
while(1) {
if (TIFR1 & (1 << OCF1A)) { // when comparison has occured, bit OCF1A is set
// -> "The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request" : 16.2.1 Register
// -> bit OCF1A is in register TIFR1 : 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
// -> 16.2.1 : "The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request"
// -> 16.11.9 : bit OCF1A is in register TIFR1
TOGGLE_LED(D2); // toggle using PINx register
TIFR1 = (1 << OCF1A); // clear the CTC flag
// -> "OCF1A can be cleared by writing a logic one to its bit location" : 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
// -> 16.11.9 : "OCF1A can be cleared by writing a logic one to its bit location"
}
}
}