31 lines
1.4 KiB
C
31 lines
1.4 KiB
C
#ifndef USART_H
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#define USART_H
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#define BAUD_PRESCALER(usart_baudrate) (DIV_ROUND_CLOSEST(F_CPU, (16 * usart_baudrate)) - 1)
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// Table 20-8 : Mode Selection (USART Mode SELect)
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#define ASYNCHRONOUS (0<<UMSEL01 | 0<<UMSEL00)
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#define SYNCHRONOUS (0<<UMSEL01 | 1<<UMSEL00)
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// Table 20-9 : Parity Bit Selection (USART Parity Mode)
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#define PARITY_DISABLED (0<<UPM01 | 0<<UPM00)
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#define PARITY_EVEN (1<<UPM01 | 0<<UPM00)
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#define PARITY_ODD (1<<UPM01 | 1<<UPM00)
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// Table 20-10 : Stop Bit Selection (USART Stop Bit Select)
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#define STOP_ONE_BIT (0<<USBS0)
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#define STOP_TWO_BIT (1<<USBS0)
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// Table 20-11 : Data Bit Selection (USART Character SiZe)
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#define DATA_FIVE_BIT (0<<UCSZ02 | 0<<UCSZ01 | 0<<UCSZ00)
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#define DATA_SIX_BIT (0<<UCSZ02 | 0<<UCSZ01 | 1<<UCSZ00)
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#define DATA_SEVEN_BIT (0<<UCSZ02 | 1<<UCSZ01 | 0<<UCSZ00)
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#define DATA_EIGHT_BIT (0<<UCSZ02 | 1<<UCSZ01 | 1<<UCSZ00)
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#define DATA_NINE_BIT (1<<UCSZ02 | 1<<UCSZ01 | 1<<UCSZ00)
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// 20.11.3 : USART Control and Status Register B (UCSRnB)
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#define RECEIVER_DISABLED (0<<RXEN0)
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#define RECEIVER_ENABLED (1<<RXEN0)
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#define TRANSMITTER_DISABLED (0<<TXEN0)
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#define TRANSMITTER_ENABLED (1<<TXEN0)
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#define INTERRUPT_RECEIVER_DISABLED (0<<RXCIE0)
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#define INTERRUPT_RECEIVER_ENABLED (1<<RXCIE0)
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#define INTERRUPT_TRANSMITTER_DISABLED (0<<TXCIE0)
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#define INTERRUPT_TRANSMITTER_ENABLED (1<<TXCIE0)
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#endif // USART_H
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