From f0566e8bdebf6c7f8727e902a53d6285f967bcf5 Mon Sep 17 00:00:00 2001
From: hugogogo <hugogogo@protonmail.com>
Date: Fri, 7 Mar 2025 12:00:18 +0100
Subject: [PATCH] mod02 ex01 works but not clear how

---
 module02/ex01/main.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/module02/ex01/main.c b/module02/ex01/main.c
index f893ec6..7c9cbae 100644
--- a/module02/ex01/main.c
+++ b/module02/ex01/main.c
@@ -88,6 +88,7 @@
 
 // TIMER
 #define PERIOD							2000
+#define TIME_MS(ms)						(((F_CPU / PRESCALE_VALUE) * ms) / 1000)
 #define PRESCALE_VALUE					1024		// can be 1, 8, 64, 256, 1024
 // table 16-5 : prescale sets
 #define PRESCALE_SET(value)  \
@@ -137,9 +138,17 @@ int main() {
 	TCCR1A |= CTC_TOP_OCR1A_IN_TCCR1A;				// Table 16-4 : set timer in CTC (Clear Time on Compare) mode
 	TCCR1B |= CTC_TOP_OCR1A_IN_TCCR1B;
 
+	TIMSK1 |= (1 << OCIE1A);						// Enable CTC interrupt
+	sei();											// Enable global interrupts
+
 	OCR1A = TIME_MS(PERIOD);						// Table 16-4 : set CTC compare value, the counter is cleared to zero when the counter value (TCNT1) matches the OCR1A register
 
 	TCCR1B |= (PRESCALE_SET(PRESCALE_VALUE));		// 16.4 : set timer according to prescale value, in register TCCR1B, table 16-5 : prescale sets
 
 	while(1);
 }
+
+// ISR interrupt macro : https://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html
+ISR(TIMER1_COMPA_vect) {							// Table 12-7 : 
+	uart_printstr("Hello World!");
+}