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ex01 mod04 not stable

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This commit is contained in:
hugo LAMY
2025-03-10 17:27:05 +01:00
parent 768054d6c2
commit 9bae6d3f49
11 changed files with 191 additions and 3 deletions
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2
module04/ex00/bitmanip.h
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@@ -33,6 +33,8 @@
#define TEST_PIN(elem) (TEST(CONCAT(PIN, GET_PORT(elem)), GET_BIT(elem)))
#define IS_PIN_SET(elem) (TEST_PIN(elem) == 0)
#define IS_PIN_CLEAR(elem) (TEST_PIN(elem) == 1)
#define PULLUP_ON(elem) SET(CONCAT(PORT, GET_PORT(elem)), GET_BIT(elem))
#define PULLUP_OFF(elem) CLEAR(CONCAT(PORT, GET_PORT(elem)), GET_BIT(elem))
// Bit definitions
#define D1 0

2
module04/ex00/header.h
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@@ -6,9 +6,7 @@
#include <avr/interrupt.h>
#include "utils.h"
#include "timer.h"
#include "bitmanip.h"
#include "usart.h"
#include "interrupt.h"
//

37
module04/ex00/main.c
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@@ -1,8 +1,43 @@
#include "header.h"
// 14.3.3 : alternate functions on port D
// PD2 : - INT0 (External Interrupt 0 Input)
// - PCINT18 (Pin Change Interrupt 18)
// 12.4 : Interrupt Vectors in ATmega328 and ATmega328P
// - INT0 : External Interrupt Request 0
// led RGB D5 must turns on in a loop of colors using PWM
typedef enum {
DOWN,
UP
} State;
volatile uint8_t button_state = UP;
// Table 13-2 : interrupt types
#define INT0_LOW ((0 << ISC01) | (0 << ISC01))
#define INT0_LOGICAL ((0 << ISC01) | (1 << ISC01))
#define INT0_FALLING ((1 << ISC01) | (0 << ISC01))
#define INT0_RAISING ((1 << ISC01) | (1 << ISC01))
// use interruption to change led1 state when button1 is pressed
int main() {
MODE_OUTPUT(LED1);
CLEAR_ELEM(LED1);
MODE_INPUT(BUTTON1);
PULLUP_ON(BUTTON1);
SREG |= ENABLE_GLOBAL_INTERRUPT;
EIMSK = (1 << INT0); // 13.2.2 : Enable INT0 interrupt (EIMSK – External Interrupt Mask Register)
EICRA = INT0_LOGICAL; // Table 13-2 : trigger type (EICRA – External Interrupt Control Register A)
while (1);
}
ISR(INT0_vect) {
_delay_ms(50);
button_state = (button_state == UP) ? DOWN : UP;
if (button_state == UP) {
TOGGLE_ELEM(LED1);
}
// EIFR = (1 << INTF0); // 13.2.3 : clear flag, why ? i think it only indicates that a trigger event has occured
}

27
module04/ex00/timer.h
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@@ -1,27 +0,0 @@
#ifndef TIMER_H
#define TIMER_H
// table 16-5 : prescale sets
#define PRESCALE_SET(value) \
((value) == 1 ? (0<<CS12 | 0<<CS11 | 1<<CS10) : \
(value) == 8 ? (0<<CS12 | 1<<CS11 | 0<<CS10) : \
(value) == 64 ? (0<<CS12 | 1<<CS11 | 1<<CS10) : \
(value) == 256 ? (1<<CS12 | 0<<CS11 | 0<<CS10) : \
(value) == 1024? (1<<CS12 | 0<<CS11 | 1<<CS10) : \
(0<<CS12 | 0<<CS11 | 0<<CS10))
#define TIME_MS(ms, prescale_value) (((F_CPU / prescale_value) * ms) / 1000)
// Table 16-4 : Waveform Generation Mode Bit Description
#define CTC_TOP_OCR1A_IN_TCCR1B (0<<WGM13 | 1<<WGM12)
#define CTC_TOP_OCR1A_IN_TCCR1A (0<<WGM11 | 0<<WGM10)
#define CTC_TOP_ICR1_IN_TCCR1B (1<<WGM13 | 1<<WGM12)
#define CTC_TOP_ICR1_IN_TCCR1A (0<<WGM11 | 0<<WGM10)
#define FAST_PWM_TOP_OCR1A_IN_TCCR1B (1<<WGM13 | 1<<WGM12)
#define FAST_PWM_TOP_OCR1A_IN_TCCR1A (1<<WGM11 | 1<<WGM10)
#define FAST_PWM_TOP_ICR1_IN_TCCR1B (1<<WGM13 | 1<<WGM12)
#define FAST_PWM_TOP_ICR1_IN_TCCR1A (1<<WGM11 | 0<<WGM10)
// 16.11.8 : Timer/Counter1 Interrupt Mask Register
#define INTERRUPT_ENABLE_CHANNEL_A (1 << OCIE1A)
#define INTERRUPT_DISABLE_CHANNEL_A (0 << OCIE1A)
#endif // TIMER_H

31
module04/ex00/usart.h
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@@ -1,31 +0,0 @@
#ifndef USART_H
#define USART_H
#define BAUD_PRESCALER(usart_baudrate) (DIV_ROUND_CLOSEST(F_CPU, (16 * usart_baudrate)) - 1)
// Table 20-8 : Mode Selection (USART Mode SELect)
#define ASYNCHRONOUS (0<<UMSEL01 | 0<<UMSEL00)
#define SYNCHRONOUS (0<<UMSEL01 | 1<<UMSEL00)
// Table 20-9 : Parity Bit Selection (USART Parity Mode)
#define PARITY_DISABLED (0<<UPM01 | 0<<UPM00)
#define PARITY_EVEN (1<<UPM01 | 0<<UPM00)
#define PARITY_ODD (1<<UPM01 | 1<<UPM00)
// Table 20-10 : Stop Bit Selection (USART Stop Bit Select)
#define STOP_ONE_BIT (0<<USBS0)
#define STOP_TWO_BIT (1<<USBS0)
// Table 20-11 : Data Bit Selection (USART Character SiZe)
#define DATA_FIVE_BIT (0<<UCSZ02 | 0<<UCSZ01 | 0<<UCSZ00)
#define DATA_SIX_BIT (0<<UCSZ02 | 0<<UCSZ01 | 1<<UCSZ00)
#define DATA_SEVEN_BIT (0<<UCSZ02 | 1<<UCSZ01 | 0<<UCSZ00)
#define DATA_EIGHT_BIT (0<<UCSZ02 | 1<<UCSZ01 | 1<<UCSZ00)
#define DATA_NINE_BIT (1<<UCSZ02 | 1<<UCSZ01 | 1<<UCSZ00)
// 20.11.3 : USART Control and Status Register B (UCSRnB)
#define RECEIVER_DISABLED (0<<RXEN0)
#define RECEIVER_ENABLED (1<<RXEN0)
#define TRANSMITTER_DISABLED (0<<TXEN0)
#define TRANSMITTER_ENABLED (1<<TXEN0)
#define INTERRUPT_RECEIVER_DISABLED (0<<RXCIE0)
#define INTERRUPT_RECEIVER_ENABLED (1<<RXCIE0)
#define INTERRUPT_TRANSMITTER_DISABLED (0<<TXCIE0)
#define INTERRUPT_TRANSMITTER_ENABLED (1<<TXCIE0)
#endif // USART_H