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mod03 ex01 ok

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hugo LAMY
2025-03-10 10:29:26 +01:00
parent 3160435041
commit 3a1dc78544
7 changed files with 127 additions and 0 deletions
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8
module03/ex00/interrupt.h
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@@ -1,8 +0,0 @@
#ifndef INTERRUPT_H
#define INTERRUPT_H
// 7.3.1 : SREG – AVR Status Register
#define ENABLE_GLOBAL_INTERRUPT (1<<SREG_I)
#define DISABLE_GLOBAL_INTERRUPT (0<<SREG_I)
#endif // INTERRUPT_H

27
module03/ex00/timer.h
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@@ -1,27 +0,0 @@
#ifndef TIMER_H
#define TIMER_H
// table 16-5 : prescale sets
#define PRESCALE_SET(value) \
((value) == 1 ? (0<<CS12 | 0<<CS11 | 1<<CS10) : \
(value) == 8 ? (0<<CS12 | 1<<CS11 | 0<<CS10) : \
(value) == 64 ? (0<<CS12 | 1<<CS11 | 1<<CS10) : \
(value) == 256 ? (1<<CS12 | 0<<CS11 | 0<<CS10) : \
(value) == 1024? (1<<CS12 | 0<<CS11 | 1<<CS10) : \
(0<<CS12 | 0<<CS11 | 0<<CS10))
#define TIME_MS(ms, prescale_value) (((F_CPU / prescale_value) * ms) / 1000)
// Table 16-4 : Waveform Generation Mode Bit Description
#define CTC_TOP_OCR1A_IN_TCCR1B (0<<WGM13 | 1<<WGM12)
#define CTC_TOP_OCR1A_IN_TCCR1A (0<<WGM11 | 0<<WGM10)
#define CTC_TOP_ICR1_IN_TCCR1B (1<<WGM13 | 1<<WGM12)
#define CTC_TOP_ICR1_IN_TCCR1A (0<<WGM11 | 0<<WGM10)
#define FAST_PWM_TOP_OCR1A_IN_TCCR1B (1<<WGM13 | 1<<WGM12)
#define FAST_PWM_TOP_OCR1A_IN_TCCR1A (1<<WGM11 | 1<<WGM10)
#define FAST_PWM_TOP_ICR1_IN_TCCR1B (1<<WGM13 | 1<<WGM12)
#define FAST_PWM_TOP_ICR1_IN_TCCR1A (1<<WGM11 | 0<<WGM10)
// 16.11.8 : Timer/Counter1 Interrupt Mask Register
#define INTERRUPT_ENABLE_CHANNEL_A (1 << OCIE1A)
#define INTERRUPT_DISABLE_CHANNEL_A (0 << OCIE1A)
#endif // TIMER_H

31
module03/ex00/usart.h
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@@ -1,31 +0,0 @@
#ifndef USART_H
#define USART_H
#define BAUD_PRESCALER(usart_baudrate) (DIV_ROUND_CLOSEST(F_CPU, (16 * usart_baudrate)) - 1)
// Table 20-8 : Mode Selection (USART Mode SELect)
#define ASYNCHRONOUS (0<<UMSEL01 | 0<<UMSEL00)
#define SYNCHRONOUS (0<<UMSEL01 | 1<<UMSEL00)
// Table 20-9 : Parity Bit Selection (USART Parity Mode)
#define PARITY_DISABLED (0<<UPM01 | 0<<UPM00)
#define PARITY_EVEN (1<<UPM01 | 0<<UPM00)
#define PARITY_ODD (1<<UPM01 | 1<<UPM00)
// Table 20-10 : Stop Bit Selection (USART Stop Bit Select)
#define STOP_ONE_BIT (0<<USBS0)
#define STOP_TWO_BIT (1<<USBS0)
// Table 20-11 : Data Bit Selection (USART Character SiZe)
#define DATA_FIVE_BIT (0<<UCSZ02 | 0<<UCSZ01 | 0<<UCSZ00)
#define DATA_SIX_BIT (0<<UCSZ02 | 0<<UCSZ01 | 1<<UCSZ00)
#define DATA_SEVEN_BIT (0<<UCSZ02 | 1<<UCSZ01 | 0<<UCSZ00)
#define DATA_EIGHT_BIT (0<<UCSZ02 | 1<<UCSZ01 | 1<<UCSZ00)
#define DATA_NINE_BIT (1<<UCSZ02 | 1<<UCSZ01 | 1<<UCSZ00)
// 20.11.3 : USART Control and Status Register B (UCSRnB)
#define RECEIVER_DISABLED (0<<RXEN0)
#define RECEIVER_ENABLED (1<<RXEN0)
#define TRANSMITTER_DISABLED (0<<TXEN0)
#define TRANSMITTER_ENABLED (1<<TXEN0)
#define INTERRUPT_RECEIVER_DISABLED (0<<RXCIE0)
#define INTERRUPT_RECEIVER_ENABLED (1<<RXCIE0)
#define INTERRUPT_TRANSMITTER_DISABLED (0<<TXCIE0)
#define INTERRUPT_TRANSMITTER_ENABLED (1<<TXCIE0)
#endif // USART_H