From 2fd1d7d931d9a364e9667ade265f156c01c646f3 Mon Sep 17 00:00:00 2001
From: hugo LAMY <hugo.lamy@oskey.io>
Date: Fri, 14 Mar 2025 22:18:30 +0100
Subject: [PATCH] m05e00 with automatic trigger should now work

---
 module05/ex00/adc.c   |  2 +-
 module05/ex00/timer.c | 19 ++++++++++++-------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/module05/ex00/adc.c b/module05/ex00/adc.c
index d03c95a..097e7ab 100644
--- a/module05/ex00/adc.c
+++ b/module05/ex00/adc.c
@@ -17,7 +17,7 @@ void adc_init(uint8_t prescaler_value) {
 	ADCSRA |= (1 << ADIE);								 	// 24.9.2 : enable ADC Interrupt
     ADCSRA |= ADC_PRESCALE_SET(prescaler_value);			// Table 24-5 : prescaler ADC
 
-	ADCSRB = ADC_TRIGGER_TIMER_1_OVERFLOW;					// Table 24-6 : ADC Auto Trigger Source
+	ADCSRB = ADC_TRIGGER_TIMER_1_COMPARE_B;					// Table 24-6 : ADC Auto Trigger Source
 	ADMUX = (ADMUX & 0b11110000) | (adc_channel & 0b1111);	// Table 24-4 : Select ADC channel 0, (Table 14-6 : alternate function for RV1 on PC0 -> ADC0)
 }
 
diff --git a/module05/ex00/timer.c b/module05/ex00/timer.c
index 27eca83..02307d4 100644
--- a/module05/ex00/timer.c
+++ b/module05/ex00/timer.c
@@ -1,17 +1,22 @@
 #include "header.h"
 
 // Set up Timer1 in CTC mode to trigger every 20ms
-// With 16MHz clock and prescaler of 8, and OCR1A = 39999:
-// 16MHz/8/40000 = 50Hz = 20ms period
+// With 16MHz clock and prescaler of 64, and OCR1A = 49999:
+// 16000000/64/50000 = 20ms period
 #define T1B_PRESCALE_VALUE					64
 void timer_1B_init() {
 	TCCR1A = 0;											// 16.11.1 : Normal operation, OC1A/OC1B disconnected
-	TCCR1B = (1 << WGM12);								// 16.11.2 : CTC mode
-	TCCR1B |= T1_PRESCALE_SET(T1B_PRESCALE_VALUE);		// 16.11.2 : prescaler = 8
-	OCR1A = TIME_MS(20, T1B_PRESCALE_VALUE);			// 16.11.5 : Compare match value for register A
-	OCR1B = TIME_MS(20, T1B_PRESCALE_VALUE) - 1000;		// 16.11.6 : Compare match value for register B
+	TCCR1B = CTC_TOP_OCR1A_IN_TCCR1B;					// 16.11.2 : CTC mode top OCR1A
+	TCCR1B |= T1_PRESCALE_SET(T1B_PRESCALE_VALUE);		// 16.11.2 : prescaler
 
-	// TIMSK1 = (1 << OCIE1B);								// Enable Timer1 Compare B Match Interrupt
+	OCR1A = TIME_MS(20, T1B_PRESCALE_VALUE);			// 16.11.5 : Compare match value for register A
+	// OCR1B = ;										// 16.11.6 : Compare match value for register B, since not defined, should default to 0
+
+	TIMSK1 = (1 << OCIE1B);								// 16.11.8 : Enable Timer1 Compare B Match Interrupt
 
 	// ADCSRA |= (1 << ADSC);							// 24.9.2 : start first conversion
+}
+
+ISR(TIMER1_COMPB_vect) {
+    // Empty ISR to ensure proper flag clearing or something like that (p145 : "OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed")
 }
\ No newline at end of file